This invention relates to manufacturing processes used to create multilayer semiconductor circuit devices on silicon substrates. Those processes generally subject a silicon wafer to an ordered series of steps, which may include photomasking, material deposition, oxidation, nitridization, ion implantation, diffusion and etching, in order to achieve a final product.
As the area allocable to individual memory cells within a DRAM array has shrunk in the face of ever-increasing memory densities, a variety of techniques have been employed by semiconductor manufacturers to maintain cell capacitance and to minimize capacitor charge leakage. The effort has been driven by a desire to minimize cell refresh overhead and the requirement that cell capacitance be sufficient to ensure proper sensing of data by bit line sense amps--even in the presence of single event upsets such as alpha particle radiation.
One way to increase cell capacitance is to maximize the usable portion of the active regions. During the process of field oxidation, oxide encroaches beneath the silicon nitride layer which is used to protect the cell's active regions. A number of processes have been developed to reduce this encroachment. Each of the processes has its advantages and disadvantages, and most add a great deal of complexity to the manufacturing process.
A key technique for reducing field oxide encroachment into the active regions is that of Local Encroachment Reduction (LER). Developed by Tyler Lowrey of Micron Technology, Inc., the technique consists of selectively etching a predetermined portion of the field oxide present within the array's active regions and then subjecting the active regions (including the etched areas) to a high-energy boron implant in order to maintain adequate active area isolation. The boron implant also doubles as a capacitance-enhancing technique.
The boron implanting technique, or so-called "Hi-C" process, consists of implanting boron ions below the array's active regions. The process has been widely used in DRAM manufacturing to increase cell capacitance and improve refresh characteristics by reducing the width of the depletion region between the n+ active regions and the p substrate and by creating a substrate gradient which functions as an electrical barrier to capacitive-charge-destroying migrating holes. DRAM cells which have received "Hi-C" implanting demonstrate a markedly reduced susceptibility to alpha-particle-generated soft errors.